a. Field of the Invention
The present invention relates generally to passing voice communications over a data communications network such as an asynchronous communications network or a synchronous communications network.
b. Background Information
Almost all customers of data traffic today have additional, separate links to carry voice. This is inefficient for the customer and the communications provider (or carrier). Many are seeking techniques that place Ds0 (or voice) channels in data packets for transmission over a data link, so that they can remove their voice links.
A communications network serves to transport information among a number of locations. The information is usually presented to the network in the form of time-domain electrical signals and can represent any combination of voice, video, or computer data. A typical communications network consists of various physical sites called “nodes,” interconnected by conduits called “links.” Each link carries information from one site to another site. End user sites may contain data terminating equipment (DTE) for combining, separating, and transforming data with or without voice. Network provider sites usually include either edge switches, with user network interfaces (UNI), or backbone switches, which only connect to other backbone switches and, edge switches and do not contain UNI.
Voice information is carried via a Ds0 channel that is a 64 kilobits per second (64 Kbps) channel and also the worldwide standard for digitizing voice conversation. The channel throughput is 64 Kbps because a digital data stream can adequately represent an analog voice signal if sampled at a rate of 8000 samples per second. If each voice sample is digitized using 8 bits, this results in a digital data stream of 64 Kbps. Since Ds0 is a synchronous TDM (time-division multiplexing) link, once a channel connection has been setup between two users, that channel is dedicated until the connection is torn (or brought) down, and cannot be used by anything or anybody else even if there is silence in the line.
Data currently is transmitted between nodes either as synchronous or asynchronous. In a synchronous network using Synchronous Transfer Mode (STM), each timeslot is assigned a certain time when it is to arrive at each node. The time when the timeslot arrives determines where the timeslot goes. Thus, the individual timeslots do not need to have routing information within them.
Asynchronous Transfer Mode (ATM), Frame Relay (FR), and Internet Protocol (IP) are considered asynchronous protocols because each node in the network does not know until after a data packet arrives where it is intended to go. The arrival of a particular data packet at a node, on the other hand, is not guaranteed to occur at a particular point in time. Only by analyzing the routing information in the header can the data switch know where to route the data packet.
ATM is designed to be carried over the emerging fiber optical network, called the Synchronous Optical NETwork (SONET), although it can be carried over almost any communications link. The basic unit of ATM is a data packet called the ATM cell. Each cell contains two parts, a header, which contains routing information, and a payload, which contains the data to be transported from one end node to another. The ATM cell is always the same size.
Frame Relay (FR) and Internet Protocol (IP) are communications protocols. Each is similar to ATM in that they also consist of a data packet. However, they differ from ATM in that their packet size can vary from packet to packet, and both can be considerably larger than ATM. This allows them to make more efficient use of the bandwidth of the communications media they travel over, but it makes receiving them more difficult in that the packet size must be calculated for each packet. Both the FR and IP may be used in point to point connections, but IP may also be used when multiple ports are connected to a single transmission medium.
Data can consume as much or as little as is needed for carrying actual traffic, because data does not reserve a fixed amount of bandwidth per link. While voice will never overload, or oversubscribe, the capacity of its links, there are mechanisms in place to handle data overloads when the amount to be transmitted is more than a physical link can carry. It is these mechanisms that allow data network designers to specify more data demand than capacity to carry, which is a process called statistical multiplexing.
Statistical multiplexing is the concept of giving multiple customers, in sum total, more bandwidth through a physical connection than the physical connection can carry. This is also known as over-subscribing. Studies have shown that customers will not always use all of the bandwidth their carrier has set aside for them. It is during this period of non-use by a customer that spare bandwidth is available for over-subscription. If sufficient numbers of customers are placed on a single physical connection, then large quantities of spare bandwidth can be realized.
When traffic is isolated among two or more physical connections, less statistical multiplexing can occur, as customers on one connection cannot use spare bandwidth on another connection. By joining more customers into a single, large connection, better statistical multiplexing occurs and the carrier is able to sell more bandwidth on one high-speed physical connection than on several smaller connections whose sum is equal to the one high-speed connection.
There are different ways of handling overloads in the data network. In ATM, the network is designed with large buffers that absorb the excess traffic, queueing it up until capacity is available to place the traffic through the network. The traffic that is delivered out of its buffers first is determined by the quality of service (QOS) the customer has paid the carrier to provide. Higher QOS traffic is removed from its buffers before lower QOS traffic. This is important for real time applications such as voice or interactive TV services, which must get through the network with a minimum amount of delay.
In those instances where so much excess traffic is delivered that the network cannot queue it up in buffers, the lower QOS traffic is deleted, or dropped, from the buffers to make room for higher QOS traffic to be queued up. Ideally, customer end-to-end protocols will detect this loss of traffic and will re-transmit the lost information.
An emerging standard in the IP network uses a different approach to handling overloads. In IP, there is no QOS as in ATM. Once a data packet is injected into the IP network, it will be given equal priority with all other traffic and delivered to its destination with a minimum of delay.
In an IP network, the traffic density in a link is closely monitored. As it begins to approach the link capacity, the IP data switch sends congestion notices back towards the data sources telling them to slow down the amount of data they send. Each notice will, for a limited length of time, force the data source to restrict what it sends out. As link traffic gets closer and closer to link capacity, more of these messages are sent backwards. When an IP switch receives congestion notices and reduces the rate of transmission, it may experience congestion as well and will send congestion notices back to its sources.
Eventually, the notices reach the traffic origins and/or customers. The customer premise equipment must then cut back on what is sent into the network, and must decide which traffic it puts out has the highest priority so that it goes out while the lower priority traffic has to wait. Thus, the IP network passes the job of determining traffic priority to the customer. If a customer has a great deal of high priority traffic, it may pay a premium to not receive as many congestion notices when congestion hits the network as another customer may pay, so that it will get more guaranteed traffic during congestion.
The IP data switches also usually maintain small buffers, but these are designed exclusively to handle the small, temporary overloads that occur until the congestion notices are responded to and reduced traffic flows into the switch.
These two different means of determining traffic priority are given as an example only. Whatever the mechanism, voice will usually be given a higher priority than data. By ensuring that the voice traffic does not physically exceed the capacity of the network links, the network systems engineering team can ensure all voice gets through, squeezing out the needs of data traffic. This allows the physical links to stay at or close to capacity even as the demands of Ds0 change. This spreads the cost of the links out over more traffic, reducing the cost per data packet and thus making the network more efficient than dedicated links carrying voice alone can be.
Each of ATM, FR, and IP has certain benefits and certain disadvantages. By utilizing these protocols in areas where their benefits can be utilized to the maximum efficiency while minimizing the losses incurred from their disadvantages, a more efficient network is realized.
Because of its fixed sized packet, ATM is more attractive on the higher speed links where it is considerably less expensive to design hardware to receive a fixed sized packet than a variable sized packet. On the lower speed, but higher per-bit cost links, FR and IP are more attractive because of their line utilization efficiency. At these lower speeds, the cost difference between a port that can receive variable sized packets versus one that only has to receive fixed size packets is usually more than offset by the fact that there are no segmentation and reassembly functions that have to be performed. Segmentation and reassembly, both of which are discussed later, are needed when a variable sized message is placed in multiple data packets, which is necessary with ATM.
Improvements in the state of the art of design technology are making the segmentation and reassembly functions less expensive. On the other hands, similar improvements are making it easier to design IP and FR receivers that can operate at SONET rates. What will likely happen is that the industry will see ATM, which is maturer than IP, dominate the high-speed market for the next 5 to 10 years. After that time period, IP, which has a simpler and less expensive congestion management scheme than ATM, most likely will become the dominant mechanism in high-speed traffic.
Procedures have been developed that allow the packets carried by one protocol to be translated into other protocols, because of the existence of different protocols for transferring data packets between nodes. To date most efforts have evolved around carrying IP or FR traffic over ATM, mainly because ATM has a mature, accepted standard for carrying different traffic types over the same, high speed fibers. However, it is theoretically possible to have a situation where a data packet of any protocol may be carried by another protocol.
Conversions between these protocols usually will follow one of four procedures, each of which require processing resources to occur. The first procedure is segmentation, which involves breaking large payloads into smaller payloads for inclusion in smaller packets. The second procedure is reassembly, which involves putting segmented payloads back together into their original payload. The third procedure is encapsulation, which involves adding additional overhead to a payload to transport the payload through a medium or protocol that otherwise could not handle the payload. The fourth procedure is extraction, which involves removing the encapsulation from an encapsulated payload after it has been transferred to its destination.
Segmentation occurs when the protocol to be converted into has smaller payloads than the protocol being converted from. In segmentation, the data packet is broken up into a series of smaller packets, each of which is just large enough to fit into the payload of the converted to protocol. If overhead is added to each segmented part of the packet, then the individual segments are even smaller to make room for the overhead.
An example of such segmentation is the conversion of a FR packet into ATM Adaptation Layer (AAL)-3/4. In AAL-3/4, the 48-byte payload of the ATM cell will carry 4 bytes of overhead and 44 bytes of the segmented data packet. AAL-3/4 contains overhead that identifies if the ATM cell carries the first segmented packet, neither the first nor last (i.e., a middle packet), the last segmented part of a packet, or, if the FR packet happens to be small enough to fit entirely in a single ATM payload, the only segmented part of a packet.
A more efficient AAL technique is called AAL5 (or the Simple Efficient ATM Layer (SEAL)). In this technique, the ATM cell header has a reserved code word that can take one of two states. The cell is either the last cell of a packet, or it is not the last cell of a packet. All 48 bytes of the payload can carry segmented parts of the packet without any overhead. The start of a new packet is indicated when a non-last ATM cell immediately follows a last ATM cell, indicating that a new packet has occurred. When the final segment of a packet arrives, it will be carried in a last cell of a packet type ATM cell. If the packet happens to be small enough to fit entirely in a single ATM payload, then the cell that carries that packet will be an end of packet cell and will have followed another end of packet cell.
IP takes a similar approach to segmentation. It has built into its header information on the segmentation process, and thus can segment itself as it is passed along. This is primarily to benefit IP routing nodes that cannot handle large IP packets. These nodes will break a large packet up into smaller packets before processing them. Although other nodes can reassemble these packets back together again, because they are already in IP format they usually just continue to pass them on to the next node, leaving the entire reassembly process up to the final destination. This process can also break IP packets (which can be in excess of 65,000 bytes in length) into smaller packets that can be carried by a frame relay packet, which is limited to packets slightly larger than 8,000 bytes.
Any protocol whose packet size is smaller than the packet size of another protocol it will carry will need to employ some form of segmentation to carry the other protocol.
Reassembly is the opposite of segmentation. In reassembly, a segmented data packet is removed from the payloads of the protocol that was carrying it and reassembled into its original form.
Reassembly is especially useful when converting from ATM to FR or IP, because many FR and IP receivers have a limited amount of packet processing capability. Numerous, small packets could overwhelm individual FR or IP receivers. By having the node that is converting from ATM to FR or IP reassemble the packet from the payloads of the ATM cell, the receiving end that subsequently gets those packets will have fewer packets to process than it took ATM cells to carry the packet to the converting node.
In encapsulation, a packet to be carried over another protocol is placed inside the overhead of the protocol to make it conform to the carrying protocol's standards. Two examples of encapsulation previously discussed are: 1) the AAL-3/4 cell that carries the only segmented packet of a data packet; and 2) the AAL-5 cell that carries the last cell of a segment and immediately follows another AAL-5 cell that also carried the last as cell of a segment.
Most IP data packets are nowhere near their maximum capable size and for this reason can be easily encapsulated in a FR packet.
Extraction is the opposite of encapsulation. The encapsulation is stripped away to reveal the original packet. For instance, a local area network (LAN) using IP based traffic sends a packet bound for a distant destination to its edge router or customer premise equipment (CPE). The CPE uses FR to communicate to the network, so it encapsulates the IP packet into a FR packet for transmission into the network. At the other end the FR layer around the IP packet is removed, thus extracting the IP packet to be sent to its destination.
There are a variety of conduits to transport or move data packets between two locations with each way having particular features. On a bit per bit basis, it is significantly less expensive to transmit data over fiber than using metallic links by several factors of ten. The theoretical capacity of fiber is in excess of 20 tera bits per second (20 million million bits per second). Current standards are 10 thousand million bits per second (gigabits per second or gbps), and will soon increase to 40 thousand million bits per second. Furthermore, technology is also improving on the ability of a single fiber to carry numerous wavelengths or colors. Each wavelength can carry 10 gbps independently of what the other wavelengths in the fiber are doing.
On the other hand, metallic links that can span long distances and are reasonable to manufacture have long ago reached their theoretical limits of roughly 500 million bits per second. They are much bulkier than fiber optic links. The metallic link is also susceptible to rust and corrosion, whereas the fiber optic link is relatively chemically inert.
A T1 link, which is an example of a metallic link, transmits one T1 frame 8000 times per second (or one frame every 125 μs). Each T1 frame contains a T1 payload with 24 Ds0 timeslots, one for each Ds0 channel with 8 bits in each timeslot. Each T1 frame also has a T1 frame bit that identifies the start of the T1 frame, so that a T1 frame has a total size of 193 bits. This results in a data stream of 1.544 Mbps (8000 frames/sec·193 bits/frame).
Repeaters, which re-amplify the signal, are needed to prevent signal attenuation (loss of signal strength as a signal travels down a link) on either type of link. Metallic links attenuate the signals more than do fiber optic links, so more repeaters for metallic links are needed than for fiber optic links for a given distance. For instance, a T1 link can span a maximum of just over one mile (6000 feet) before a repeater is needed; for T3, the range is less than 1400 feet. It is not unusual for fiber optic links to span 50 to 100 miles between repeaters. Fiber optic links also cost less per foot physically than metallic links do, and the connectors at each end of a fiber optic link are similar in price to the connectors of a metallic link. Given the longer span between repeaters, this translates into fewer connectors, and hence lowers the cost, for fiber optic links.
While metallic interfaces on port cards and repeaters are less expensive than fiber optic interfaces, the cost difference does not justify the reduced number of repeaters in a fiber optic network, nor does it justify the more expensive cabling needs even inside a switching facility. Further, the limited range of T3 metallic links has impacted the designs of several switching facilities, whereas the range of fiber optic links does not factor into their design.
c. Related Art
A data switch routes data packets from incoming ports to outgoing ports through a data switching matrix usually using an identification number. The concept of the identification number associated with the carrying of a data packet within a data switch is a commonly used technique to indicate to other node components the destination port card for the data packet. Most such identification numbers are nothing more than series of bits that specify the outgoing port(s) the data packet is destined for and a priority level for determining what queue it should be stored in until departure. The identification number does not effect the processing of the data packet or whether the data packet will be changed to accommodate the native protocol being used by different node components.
There are numerous designs for data switch matrices of which only two will be discussed below.
One data switching matrix is a dedicated matrix that receives data packets from every incoming port card (or port interface), buffers them, and then routes them to their intended outgoing data port. Because multiple incoming packets may be destined for each outgoing data port, the links to the outgoing ports contain buffers in them that allow the data packets to accumulate until they can be delivered to the outgoing port card.
Another design uses a high-speed backplane as the delivery mechanism and circuits on each port card to examine, then accept or reject each packet. This scheme is easier to implement, but requires advanced technology to deliver high data volumes from all incoming ports to all outgoing ports. Such technologies, including low voltage differential swing (LVDS), have recently become available.
Regardless of the method used, the data switching matrix can deliver a data packet from any source to any destination. Nor is the data packet limited to a single destination. Sending a data packet to multiple destinations is called multi-casting or broadcasting. Applications that might use this feature would be updates of database copies to allow local access to the database in different, distant areas, the transmission of entertainment services to multiple destinations, etc.
A data switch cannot switch individual Ds0 channels within a data packet unless a Ds0 switch with a Ds0 switching matrix is added to the data switch. Presently, there are two primary architectures for placing a Ds0 switch in a data switch.
The first concept places the Ds0 switch inside the data switch such that it does not occupy the physical space of an external port, but it consumes resources from the data switch as if it were an external port card. As a result, the Ds0 switch still consumes a port interface that reduces the number of external ports the matrix can otherwise support. Many designs call for installing a large Ds0 switching matrix in the slot of a port card or some other means of having the Ds0 switching matrix attach to the data switching matrix in a fashion similar to a port card. Such Ds0 switches consume resources and bandwidth within the data switch that reduces the number of port interfaces available to the data switch, increasing the costs per port of the remaining port interfaces on the data switch. A centrally located Ds0 switching matrix must be able to handle large quantities of Ds0 channels concurrently, which requires a great deal of bandwidth out of the data matrix, and a larger amount of memory than if the load is shared across each port card. The alternative to a large Ds0 switching capacity is to limit the Ds0 switching capacity of the data switch to a small fraction of the overall capacity of the data switch.
Existing designs are inefficient in a number of areas. In one area, any Ds0 channel that has to be extracted from a data packet passes through the data switching matrix twice. This is because the Ds0 switching matrix is designed as an afterthought, and takes on the appearance of another port card in the data switch. Thus, the first time the Ds0 channel passes through the data switching matrix is when it is routed to the Ds0 switching matrix. The second time occurs after the Ds0 switching matrix has extracted the Ds0 channel, switched it around, and then placed it into a new data packet and returned it to the data switching matrix to be routed to the appropriate outgoing port.
The second concept places the Ds0 switch on the port card sequentially between the incoming port and the connection to the data switching matrix to provide processing for information flows entering the data switch only. This concept solves the efficiency problems stated previously. However, this concept makes it impossible to combine Ds0 channels from different incoming ports into a single data packet. In data switches carrying a large amount of Ds0 traffic, this approach may lead to several problems. The first problem is that the likelihood of blocking, or the inability to find, a dedicated 64 kbps Ds0 path through the switch increases. Second, this inability to combine incoming Ds0 channels leads to the creation of many smaller data packets, which increases demand on the header processing circuitry of the network if the data packets are of variable size, or the creation of data packets with unused payload space if the packets are of a fixed size. Third, the inability to combine Ds0 channels may lead to latency, or the addition of more delay, between the source and the destination of a Ds0 channel. For instance, round trip delays starting around 140 ms, and definitely in excess of approximately 200 ms or more will affect the spontaneity of a conversation. With the inability to bundle all Ds0 channels together, more data switches must process the Ds0 channels through their Ds0 switching matrixes, increasing delay. Fourth, this design does not lend itself easily to combining channels together to maximize the use of switch and network resources, to testing, and to decreasing delays for Ds0 traffic. Fifth, the design prevents reasonable path verification and bit error rate (BER) tests on the Ds0 switching matrix.
Ds0 switching nodes (Ds0 switches) contain a switching matrix that is used to route Ds0 samples from any timeslot of any incoming link to any timeslot on any outgoing link. An example of such a switching matrix is a single stage Time Slot Interchange (TSI) matrix. A TSI matrix places all incoming Ds0 samples from all incoming links into predefined locations in a randomly accessible memory (RAM). This RAM is frequently referred to as the data RAM. Many designs also place in parallel with the Ds0 channel internal status concerning the Ds0 channel in the same location in the data RAM.
A second RAM, called a control RAM, contains connection information and is used to provide a lookup address into the data RAM. Each location in the control RAM represents what an outgoing timeslot on a particular outgoing link will carry. Each location in the control RAM will address a location in the data RAM, and thus connect a particular incoming timeslot of an incoming link with an outgoing timeslot of an outgoing link. The control RAM may also possess additional control bits associated with the outgoing timeslot.
The contents of the control RAM are read out in a predetermined pattern. By following this pattern, internal timing designs within the node will assure that the intended incoming timeslot represented in the data RAM is presented to the intended outgoing timeslot.
The most efficient design for a TSI switching matrix is achieved when all Ds0 channels can be physically stored in a single RAM. If the number of Ds0 channels exceeds the limits of a single RAM, then the amount of RAM needed is the square of the number of RAM needed to store all the Ds0 channels once. This is because the job of selecting outgoing channels has to be split up among two or more identical circuits. Each outgoing circuit needs its own dedicated copy of each incoming channel in order to function without any possibility of contention occurring between it and another outgoing circuit for the same data RAM.
Today's state of the art can write or read (access) a RAM approximately 16,384 times (16K; “K” denotes 1024, or 210) in a 125 μs time period. If there are 32K Ds0 channels, then four memories are needed. Two RAMs are needed to store all 32K channels, splitting the channels between the two RAMs. This number must then double because there will be two outgoing circuits and each needs all 32K incoming channels available to it; therefore each incoming channel has to be duplicated into two sets of RAMs. If there were 48K channels there would have to be nine sets of RAMs, and if there were 64K channels there would have to be 16 sets of RAMs. There are a variety of schemes for Ds0 switching matrix design beyond this example.
Another area existing designs are inefficient in is that in order to handle large numbers of Ds0 channels to take advantage of the statistical multiplexing of a large, integrated network, a large switching matrix on the order of 256K to 1024K Ds0 channels must exist in the switch. This large matrix must take in large amounts of data packets, break out the Ds0 channels within them, route them through the matrix, make new data packets, and send them back through the switch to the destination port. As stated earlier, current Ds0 switching technology can only access a RAM 16K times in a 125 μs time period. Because of the squaring problem discussed earlier, a 256K Ds0 channel matrix would take 256 data RAMs to provide for a TSI switching matrix to handle all connections.
Where a data switch is adapted to route different types of packets concurrently, i.e., ATM, Frame Relay, or Internet Protocol, the design of the switch is such that only one type of packet is switched, and the other packet formats are converted into the designated format for switching. However, this leads to inefficiencies when port cards, which carry packet types that are not native to the switching matrix of the data switch, must convert the packet type of that port card to the designated packet format of the switch. When two such port cards are passing packets between themselves, they must convert to the other protocol, and then re-convert back to their own format. This introduces additional time delays and packet handling complexities throughout the communications network. It can also increase the amount of traffic carried in the data switching matrix by more than would otherwise be carried if the switching of packets occurred in the format of the port cards. In the case of IP packets or other protocols that can self-segment, the process can result in numerous smaller IP segments that increase the workload of a downstream communications node.
Another problem for the industry is that if a new protocol for the backbone transmission of data packets is developed, the conversion of the new protocol to the protocol of existing switches will result in inefficiencies carrying that protocol through the switching node. This also increases the bandwidth consumed through the switching matrix to pass certain amounts of data through the node. Many existing nodes would have to be replaced.
Notwithstanding the usefulness of the above-described voice switching matrices and port cards, a need still exists for placement of a Ds0 switch with a Ds0 switching matrix on a port card so that a node in a communications network will more efficiently handle voice communication. A Ds0 switching matrix is needed that is capable of reducing the processing load on a data switching matrix and attached port cards. Furthermore, an identification numbering system is needed to reduce the processing load on the node components and the transmission time of data packets in a format not native to all nodes within a communications network.